Improvements in the size, formation, density, and packaging of integrated circuits (“ICs”) have led the semiconductor industry to experience rapid growth. Improvements in integration density have led to decreased IC feature size, which allows more components to be integrated into a given area.
One improvement to increase circuit density is to stack two IC dies on top of each other to form what is referred to as a three-dimensional (“3D”) IC. In a typical 3D IC formation process, two dies are bonded together and electrical connections are formed between each die and contact pads on a substrate. For example, two dies are bonded on top of each other with the lower die being coupled to a substrate. Through vias (“TVs”) in the substrate connect the dies to conductive pads on an opposing surface of the substrate. The conductive pads can then be electrically coupled to a printed circuit board (“PCB”) or the like using electrical connections.
Another 3D package which increases circuit density is referred to as a “Package-on-Package” (“PoP”) structure, wherein multiple dies coupled to respective substrates can be “stacked” on top of each other and coupled together. To form a PoP structure, a first die is electrically coupled to a first substrate to form a first circuit. The first circuit includes first connection points for connecting to a second circuit. The second circuit includes a second die and substrate having connection points on each side of the substrate. The first circuit is stacked and electrically coupled on top of the second circuit to form the PoP structure. The PoP structure can then be electrically coupled to a PCB or the like using electrical connections.
Memory circuits are stacked in 3D ICs with various other circuit components to form memory modules. Such memory modules can often include logic circuits, one or more processors, or one or more application processor units (“APUs”), which might be developed as user defined application specific integrated circuits (“ASICs”). Memory modules disposed in 3D ICs typically include an APU coupled to a substrate with TVs connecting the APU to solder pads on an opposing surface of the substrate. The TVs increase the overall height of a 3D IC as well as the design and manufacturing complexity of the 3D IC. The TVs also lower throughput for a memory circuit.